In a multiprocessor computer system, requests for data (a data transfer) by each processor are processed by a bus interface unit, which receives or sends information relating to ensuring the correct data is sent (transferred) the correct processor. A data transfer transaction goes through several stages in the computer system before the data transfer transaction is complete. Since stages from different requests may be intermingled it is difficult to keep track of all request stages of all requests through the command processor of the computer system. It is especially difficult in systems that do not enforce strict command packet order or in systems that allow command packet retry. This difficulty translates into the design phase of a computer system, specifically the simulation and verification of the command issuing logic of the design phase. During simulation of the system design it must be verified that each data transfer completes and that the appropriate data is being sent to each processor in the system. Therefore, there is a need for method and system for verification of multiple priority issue queue data requests that is robust and independent of when various stages of a particular request occur in time during the simulation of a computer system design.